The present application claims the benefit of and priority to a pending provisional patent application entitled “Grating and Trim Masks to Produce Critical Dimensions in Semiconductor Fabrication,” Ser. No. 61/618,634 filed on Mar. 30, 2012. The disclosure in that pending provisional application is hereby incorporated fully by reference into the present application.
As semiconductor devices, such as bipolar transistors, continue to decrease in size, smaller critical dimensions (CDs) are required for features within the devices. Advanced lithography techniques currently include 193 nanometer (nm) wavelength (deep ultraviolet or DUV) lithography and immersion lithography, for example. While such advanced lithography techniques may be applied to both bipolar transistors as well as CMOS transistors, the benefit in bipolar transistor performance does not outweigh the high cost involved with developing the sub-micron lithography techniques used in advanced CMOS nodes, for example, at or below the 45 nm node.
Traditional lithography techniques utilizing 248 nm deep ultraviolet exposure are sufficient to produce the line widths necessary to create satisfactory bipolar devices operating at up to 200 GHz. However, as the frequency of unity power gain Fmax for a particular transistor is driven past 200 GHz, the CDs of key features as well as their tolerances become more difficult to achieve. Specifically regarding bipolar transistors, the width of the collector implant window underneath the intrinsic emitter, and the width of the emitter poly contact pedestal above the intrinsic emitter, must be reduced as much as possible.